The present invention relates to the manufacture of semiconductor devices with fins, and more particularly, to an SRAM design to facilitate single fin cut in a double sidewall image transfer process for the 10 nanometer (nm) technology nodes and beyond.
A fin-type field effect transistor (FinFET) is a type of transistor that has a fin, containing a channel region and source and drain regions. A double-gated FinFET is a FinFET with gate conductors on both sidewall of the fin. A triple-gated FinFET is a FinFET with gate conductors on both sidewall and the top wall of the fin. The gate conductors cover the channel region of the fin, whereas the source and drain regions of the fin extend beyond the coverage of the gate conductors. FinFETs are discussed at length in U.S. Pat. No. 6,413,802 to Hu et al. (hereinafter “Hu”), which is incorporated herein by reference in its entirety. FinFETs may comprise only front and/or back gate conductors. Front gate conductors are generally isolated from any conductive material in the substrate and contacts to front gate conductors are etched from above. Back gate conductors are generally electrically connected to a conductive material in the substrate and contacts to the back conductors are etched from below. In order to improve upon current technology, manufacturers are continuously striving to increase the density of devices on integrated circuits and to simultaneously decrease the cost of producing the integrated circuits without adversely affecting performance.
To scale fin pitch to less than or equal to 40 nm, a double sidewall image transfer (SIT2). To scale fin pitch to less than or equal to 40 nm, a double sidewall image transfer (SIT2) or a self-aligned quadruple patterning (SAQP) process can be utilized. This process generates paired fins with a spacing determined by the width of the sidewall spacer that forms a second mandrel. The spacing being the two paired fins is minimized as much as possible. For some circuits, such as an SRAM bitcell, one needs to remove one of the fins in the pair, i.e., a single fin cut, as they are not intended to be part of the final FinFET devices that are formed on the substrate. The single fin to be cut is referred to as a dummy or inactive fin (i.e., FINI) and the other fin is referred to as an active fin (i.e., FINA), wherein the fin pair collectively is at minimum spacing. That minimum spacing can oftentimes be too small as a function of scaling to allow the effective removal of the FINI without damaging or removing its neighboring FINA.